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Semiconductor · sourced direct from Cisco

Semiconductor at Cisco.

Cisco currently has 63 open semiconductor roles, concentrated in San Jose, Bangalore and Pune (2 hybrid), a mix of mid- and senior-level. Apply at the source — RoleSuite links straight to Cisco's official careers page, no intermediary.

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Open semiconductor roles

63 roles

FPGA DeveloperLysaker, Norway ASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 12+ years, BangaloreBangalore, India Design Verification Engineering Lead - Silicon OneSan Jose, California, US ASIC Design Verification EngineerSan Jose, California, US ASIC Design Verification Engineer - 5 years to 13Years - BangaloreBangalore, India ASIC Engineering Technical Leader - EmulationSan Jose, California, US ASIC Design Verification Emulation EngineerSan Jose, California, US ASIC Design Verification EngineerSan Jose, California, US ASIC Engineering Technical LeaderBangalore, India ASIC Design Engineering Technical LeaderSan Jose, California, US ASIC Engineer - SDCSan Jose, California, US ASIC Design EngineerSan Jose, California, US Design Verification Engineer - Acacia NetworksHolmdel, New Jersey, US ASIC Design Engineer Technical LeadSan Jose, California, US ASIC Engineering Technical Leader- DFTSan Jose, California, US ASIC Design Verification EngineerSan Jose, California, US ASIC Design Verification EngineerSan Jose, California, US ASIC Physical Design Technical LeadSan Jose, California, US Full-Chip Physical Design EngineerArmenia ASIC Design Verification Technical Leader - Acacia (hybrid)Austin, Texas, US Physical Design ManagerCaesarea, Israel Analog/mixed-signal IC Design Developer (Hybrid)Kanata, Ontario, Canada ASIC Engineering Technical Leader (Onsite)San Jose, California, US Analog Layout DesignerCaesarea, Israel Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)San Jose, California, US ASIC/SoC Physical Design Engineer - 7 to 10 years - PunePune, India ASIC DFT Engineer || DFT/ATPG/MBIST/SCAN/JTAG || 8+ yearsBangalore, India FPGA HW Engineering Technical LeaderSan Jose, California, US ASIC Packaging Signal Integrity Hardware Engineering Technical Lead (Remote)San Jose, California, US ASIC Design Verfication Engineer II (Full Time) - United StatesSan Jose, California, US ASIC Design Verification Engineering Technical LeaderSan Jose, California, US ASIC Design Verification Engineering Technical LeaderSan Jose, California, US ASIC EngineerZhubei, Taiwan ASIC EngineerArmenia ASIC Engineer || Design Verification || Exp 8+ YearsBangalore, India ASIC Engineering Technical LeaderNuremberg, Germany ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)Pune, India ASIC Packaging Development Technical LeaderTaipei, Taiwan ASIC DFT Engineer - 4 to 8 yrsBangalore, India ASIC DFT Engineer - 7 to 10 yrsBangalore, India ASIC Design Verification EngineerSan Jose, California, US Component Engineer - Semiconductor DevicesSan Jose, California, US ASIC EngineerBangalore, India ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)Pune, India ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)Pune, India Physical Design Engineer II (Full Time) - United StatesMaynard, Massachusetts, US ASIC Physical Design EngineerMaynard, Massachusetts, US CAD/Methodology Physical Design Team LeadBangalore, India ASIC DFT Engineering Technical Leader | Scan, ATPG, MBISTBangalore, India ASIC Engineering Technical Leader- STASan Jose, California, US

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