SemiJobs
RoleSuite
CompaniesRemoteAboutMethodologyContactPrivacy
Updated 2026-06-09 23:00 UTC·© 2025–2026 RoleSuite
← Back to listings

Senior ASIC DV Engineer

Broadcom · USA-CA San Jose Innovation Drive

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include:

  • Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.

  • Using your thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests.

  • Debugging RTL and Gate simulations and work with design engineers to verify fixes.

  • Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.

  • Replicating silicon bugs in simulation environments and validating fixes or SW workarounds.

  • Converting  verification tests to test patterns and assisting  Test Engineers on ATE vector bring up.

  • Evaluating latest verification methodologies and developing scripts etc. to automate verification flows.

  • Experience understanding and verifying low power silicon for mobile applications with good knowledge of UPF low power verification flow

  • Ability to take customer requirements to verify full chip design and architecture

Qualifications:

  • Bachelors and 12+ years of related experience; or Masters degree and 10+ years of related experience; or PhD and 7+ years of related experience

  • MS or PhD is preferred 

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000. 

 

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Apply →

Other roles at Broadcom

  • R&D Engineer Physical DesignUSA-CA San Jose Innovation Drive
  • Account Director (Remote, Japan)Japan-Remote Location
  • HSIP Application EngineerUSA-CA Irvine Alton Parkway Bldg 2
  • Mainframe Licensing ConsultantNetherlands-Remote Location
  • Software Development Engineer in Test (SDET)USA-IL Lisle Warrenville Road
  • MES Software Engineer/Data AnalystUSA-Pennsylvania-Breinigsville-9999 Hamilton Blvd
  • R&D Process EngineerSingapore-Yishun
  • Senior Technical Adoption Manager (India, Bangalore, Remote)IND-Bangalore-Kalyani Vista II
  • Memory System Designer and Place and Route EngineerUSA-Mendota Heights-Northland
  • Staff Software Engineer - Intelligent Applications teamUSA-WA-Bellevue - 108th Ave

More Semiconductor roles

  • FPGA Verification Engineer, Air VehiclesAnduril Industries · Costa Mesa, California, United States
  • Traffic DesignerAlfredbeneschco · Kansas City, KS; Manhattan, KS; Overland Park, KS; Topeka, KS; Wichita, KS
  • CPU Performance Architect, SiliconGoogle · New Taipei, Banqiao District, New Taipei City, Taiwan
  • Design Verification Engineer, TPU, Silicon, Google CloudGoogle · Bengaluru, Karnataka, India
  • Design Verification EngineerGoogle · Mountain View, CA, USA
  • ASIC Formal Verification Engineer, Google CloudGoogle · Sunnyvale, CA, USA
  • CAD Physical Design EngineerApple · Cambridge
  • Senior CPU Design Verification Engineer, EmulationGoogle · Austin, TX, USA
  • Early Careers SoC Physical Design Engineer (m/f/d)Apple · Munich
  • Silicon Validation and Debug EngineerGoogle · Tel Aviv, Israel