Principal DV Engineer
Requirements
HDL & Verification Methodology
· Expert-level proficiency in Verilog and SystemVerilog
· Proven experience building UVM verification environments from scratch
· Deep understanding of verification methodologies and best practices
Programming & Scripting
· Proficient in C/C++ coding for verification purposes
· Strong scripting skills in Perl or Python
· Ability to write and maintain bash scripts for verification flows
Verification Planning & Execution
· Experience writing comprehensive test plans
· Experience writing and maintaining test suites
· Ability to debug complex RTL simulations
· Ability to debug gate-level simulations with SDF back-annotation
· Ability to assess whether SDF timing violations are benign or require attention
Leadership
· Proven track record leading code coverage closure
· Experience leading design verification efforts through chip tapeout
What you bring to this role:
10+ years of design verification experience in the semiconductor industry