Staff DV Engineer

E-Space · Saratoga, CA

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work.

Requirements

  • HDL & Verification Methodology

    · Strong proficiency in Verilog and SystemVerilog

    · Experience writing tests within an existing UVM verification environment

    · Solid understanding of UVM architecture and methodology

    Programming & Scripting

    · Ability to write C/C++ code for verification purposes

    · Some scripting experience in Perl or Python

    Verification Planning & Execution

    · Ability to contribute to and help write test plans

    · Experience writing and maintaining verification tests

    · Ability to debug RTL simulations independently

    Leadership

    · Experience leading design verification efforts at the block level

    · Experience driving code coverage closure on assigned blocks

    • What you bring to this role:

  • 6+ years of design verification experience in the semiconductor industry

    • Apply →