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Updated 2026-06-10 01:00 UTC·© 2025–2026 RoleSuite
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SoC ATE Test Engineer

Google · New Taipei, Banqiao District, New Taipei City, Taiwan

Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.

In this role, you will help develop and deploy a comprehensive test solution using Automatic Test Equipment (ATE) for high volume manufacturing. You will help integrate the System on Chip (SoC) technologies into devices and facilitate ATE manufacturing testing of SoC to validate performance and screen out devices. You will own all aspects of testing and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. Additionally, you will work with various groups to develop digital and mixed signal tests, automation methodologies, develop/support internal tools for test program generation, vector tracking, test program release, etc. You will also work on releasing cost effective production test solutions into mass production. You will work closely with foundry and Outsourced Assembly and Test (OSAT) partners.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Minimum qualifications:

  • Bachelor's degree Electrical Engineering, Computer Engineering, or equivalent practical experience.
  • 1 year of experience with ATE IC testing, yield and bin Pareto analysis.

Preferred qualifications:

  • Experience with Automatic Test Equipment (ATE) test platforms (e.g., Advantest 93K , Teradyne UltraFlex system on a chip (SoC) test system).
  • Experience with Design for Test (DFT) techniques and structural tests (e.g., Scan/ATPG, JTAG, and memory BIST).
  • Experience with system level testing using Advantest SLT platform.
  • Experience with mixed-signal circuits.
  • Familiarity with process technology, and how it relates to design and testing data analysis (e.g., wafer sort, final test).
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