Coherent NoC IP Design Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will join a team developing Application-Specific Integrated Circuits (ASICs) to accelerate machine learning computation in data centers. You will collaborate with Architecture, Verification, Power and Performance, and Physical Design teams to specify and deliver quality designs for next-generation accelerators. You will solve technical problems through micro-architecture innovation and evaluate design trade-offs between performance and power.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience designing high-speed Network-on-Chip (NoC) or fabric IP, including mesh, ring, or torus topologies.
• Experience with Verilog and SystemVerilog for RTL design and synthesis.
• Experience delivering silicon IP blocks through multiple tape-outs.

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science.
• Experience with automated NoC generation tools and custom logic design for low-power arbitration and congestion management.
• Expertise in clock domain crossing (CDC) in massive, multi-synchronous fabric environments and working knowledge of Python, Perl, or Tcl for developing design automation scripts and productivity tools.
• Knowledge of on-chip interconnect protocols such as AMBA 5 CHI, AXI5, and ACE.
• Deep understanding of cache coherency protocols (MESI/MOESI) and their hardware implementation within a fabric.
• Ability to work in the trenches with Verification teams to define coverage plans and debug complex testbench failures.