(India) System IP Design Engineer

Tenstorrent · Bengaluru, Karnataka, India

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller. You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs.

This role is Hybrid, based out of Bangalore, India.

We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting.

Who You Are

3–6 years of experience in ASIC design, with expertise in microarchitecture and RTL for complex subsystems
Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis
Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes
Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI)
Awareness of functional safety (ISO 26262) practices in hardware design

What We Need

Ability to own microarchitecture definition and RTL development of Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller
Experience driving verification closure, performance debug, synthesis, timing, and power optimization
Strong skills in LINT, CDC/RDC, and power intent checks
Proficiency with DV and analysis tools like Verdi, NCSIM, and power estimation tools
Hands-on experience in design-for-power, debug, and test methodologies

What You Will Learn

Building power-efficient, high-performance subsystems for advanced RISC-V/ARM architectures
Cross-functional collaboration from concept to silicon bring-up
Enhancing subsystem performance through innovative power, performance, and area optimizations
Leadership and mentorship experience by guiding junior design engineers

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Hardware pay context

Based on 2,221 disclosed Hardware salaries on RoleSuite, the role pays a median of $133K/year, with most offers between $109K and $171K (10th–90th percentile: $91K–$205K).

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(India) System IP Design Engineer

Hardware pay context

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