ASIC Engineer

Cisco · Taipei, Taiwan

Serve as a technical expert for advanced packaging technologies, 2.5D/3D with RDL CoW processes, large body packaging design, assembly and integration. Work directly with key suppliers to develop and enable new processes, module and material for areas of package design, assembly, integration and substrate manufacturing.

  • Engage with leading assembly suppliers to understand assembly process, module design rules and requirements.
  • Define assembly process integration and flow for advanced multiple die heterogeneous integration
  • Develop comprehensive plans of assembly and reliability to evaluate and qualify new package technologies.
  • Work closely with substrate suppliers to evaluate new materials & design rules for package warpage, stress, and SI/PI performance optimization to enable and advance product substrate physical design and implementation.
  • Work with internal package physical design team to resolve design challenges and implement working solutions using DfM/DfR principles.
  • Work with OSAT and substrate suppliers to develop practical solutions that address challenges of large body size packages and large die reticle size assembly, reliability and board-mount process.
  • This is a critical role where you will directly influence the technical direction and successful delivery of Cisco’s advanced products by driving innovative packaging and assembly solutions.

Minimum Qualifications                

  • BS/MS/PhD in Mechanical Engineering, Materials Science, Physics or a closely related field 5+ years of progressive experience in Semiconductor Packaging and Assembly Industry, with demonstrated skill and experience leading technical projects or initiatives
  • Previously proven experience in advanced packaging technology development and execution, such as 2.5D/3D process integration, heterogenous integration, wafer-level packaging, and package technology qualification method.
  • Comprehensive knowledge and understanding of advanced CoWoS package assembly and manufacturing flow.
  • Previous experience with substrate manufacturing processes, design rules and material for high layer count substrate stack-up including multi-layer core technology and impacts to device level power and signal integrity
  • Experience with package design physical attribute, material selection and package assembly process optimization for package warpage, stress and thermal performance. 

Preferred Qualifications

  • Expertise in advanced problem-solving methodologies (e.g. 8D, FMEA, statistical process control) and data analysis skills
  • Effective communication, presentation, and influencing skills, with the ability to articulate technical concepts clearly to diverse audiences.
  • Experience in package reliability for component and board level
  • Willingness to learn and evolve professionally.
  • CAD (Cadence, SolidWorks, AutoCAD) tool acknowledge is a plus

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Semiconductor pay context

Based on 255 disclosed Semiconductor salaries on RoleSuite, the role pays a median of $180K/year, with most offers between $148K and $206K (10th–90th percentile: $132K–$237K).

Cisco ranks among the higher-paying employers for this role, at a $203K median across 38 disclosed postings.

See the full Semiconductor salary breakdown →
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