TPU Compute RTL Design Engineer
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with digital design using SystemVerilog RTL.
- Experience with power, performance and area optimizations.
Preferred qualifications:
- Experience interacting with software, architecture, physical design and other cross-functional teams.
- Knowledge of processor design, accelerators, or memory hierarchies.
Semiconductor pay context
Based on 275 disclosed Semiconductor salaries on RoleSuite, the role pays a median of $180K/year, with most offers between $143K and $206K (10th–90th percentile: $130K–$237K).
Google ranks among the higher-paying employers for this role, at a $200K median across 48 disclosed postings.
This posting lists $163K–$237K, above the $180K market median.
See the full Semiconductor salary breakdown →