SemiJobs
RoleSuite
CompaniesRemoteAboutMethodologyContactPrivacy
Updated 2026-06-12 00:00 UTC·© 2025–2026 RoleSuite
← Back to listings

CPU Architecture and Performance Architect

Google · New Taipei, Banqiao District, New Taipei City, Taiwan

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a CPU architecture and performance architect, you'll be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and to deliver Google’s advanced SoC products. You’ll have the opportunity to collaborate with talents in system performance and software teams to plan and conduct application and benchmark performance analysis and to project their performance at various design phases. Leveraging your CPU-specific knowledge and leadership, you’ll be guiding junior CPU architects and working with engineers in power, thermal, security, and physical design teams to determine the CPU subsystem configuration and features.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience with high-performance microprocessor architecture, CPU microarchitecture, and workload performance analysis.
  • Experience in high-performance CPU architecture.
  • Experience with at least one area: instruction set architecture (ISA), machine learning (ML), or branch prediction.
  • Experience in performance modeling, analysis, correlation, and workload characterization.
  • Experience with C/C++ and scripting languages (e.g., Python).

Preferred qualifications:

  • PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture or machine learning.
  • 6 years of high-performance microprocessor architecture, microarchitecture, performance, and design experience.
  • Experience in leading CPU/ML performance model development, performance analysis, performance correlation, and workload characterization.
  • Deep knowledge with processor instruction set architecture (e.g., ARM, RISC-V, x86).
  • Knowledgeable on system software components, such as Linux, drivers, and runtime.

Semiconductor pay context

Based on 299 disclosed Semiconductor salaries on RoleSuite, the role pays a median of $177K/year, with most offers between $148K and $210K (10th–90th percentile: $130K–$242K).

Google ranks among the higher-paying employers for this role, at a $200K median across 48 disclosed postings.

See the full Semiconductor salary breakdown →
Apply →

Other roles at Google

  • Customer Engineer, Data/Analytics, Google Public SectorReston, VA, USA
  • Product Manager, Gemini API Models, DeepMindMountain View, CA, USA
  • Senior UX Design Manager, Search Ads UINew York, NY, USA
  • Director, Digital Demand, Scale Programs, Social, Customer AdvocacySingapore
  • Engineering Manager, PlumberNew York, NY, USA
  • Staff Software Engineer, Infrastructure, Google CloudHyderabad, Telangana, India
  • Senior Software Engineer, Infrastructure, Persistent DiskSunnyvale, CA, USA
  • Software Engineering Manager II, Google Distributed Cloud HostedSunnyvale, CA, USA
  • Senior Staff Software Engineer, Infrastructure, Google CloudSunnyvale, CA, USA
  • Software Engineer, Generative AI, MapsMountain View, CA, USA

More Semiconductor roles

  • Senior ASIC Timing Engineer, DFTNVIDIA · US, CA, Santa Clara
  • Senior Physical Design Layout EngineerNVIDIA · Israel, Yokneam
  • Senior Physical Design EngineerNVIDIA · Israel, Yokneam
  • Senior Post Silicon Validation Engineer - LPUNVIDIA · US, CA, Santa Clara
  • Physical Design EngineerNVIDIA · Israel, Yokneam
  • GPU Core Pipeline IP Verification EngineerNVIDIA · India, Bengaluru
  • ASIC Design EngineerNVIDIA · India, Bengaluru
  • Senior Power Integrity Engineer - LPU PackagingNVIDIA · Taiwan, Hsinchu
  • ASIC Verification EngineerCisco · Cairo Al Qahirah, Egypt
  • Serdes System Design Engineer/ArchitectBroadcom · USA-TX-Austin - River Place B7