SemiJobs
RoleSuite
CompaniesRemoteAboutMethodologyContactPrivacy
Updated 2026-06-12 00:00 UTC·© 2025–2026 RoleSuite
← Back to listings

Multi-Physics Simulation and Test Engineer

Google · San Diego, CA, USA

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will drive the integration, calibration, and verification of XR device hardware from early architecture through production. You will build simulations across acoustics, optics, and dynamics to virtualize and evaluate device performance before physical hardware exists. Additionally, you will define physical testing systems and build data analysis pipelines to characterize device performance and validate simulations. Finally, you will use both simulation and test platforms to generate high-fidelity datasets to develop AI/ML models. Your work will directly establish the calibration and verification methods to deliver performance for headsets and glasses across their lifetime.

For decades, the computing revolution has reshaped our world driven by
breakthroughs in compute, connectivity, mobile, and now, AI. Google's XR team is at the forefront of the next major leap – the convergence of AI and XR. This is more than just new devices – it's about reimagining how we interact with the world around us. We're building a future where
lightweight XR devices like smart glasses and headsets pair with helpful AI to augment human intelligence, offering personalized, conversational, and contextually aware experiences.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits

Learn more about benefits at Google.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
  • 4 years of experience working in a physics-based simulation technical environment.
  • Experience with physical simulation, testing, and verification, including applying multi-physics testing or simulation for acoustics, optics, or dynamics to virtualize and validate hardware behaviors.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).

Semiconductor pay context

Based on 299 disclosed Semiconductor salaries on RoleSuite, the role pays a median of $177K/year, with most offers between $148K and $210K (10th–90th percentile: $130K–$242K).

Google ranks among the higher-paying employers for this role, at a $200K median across 48 disclosed postings.

This posting lists $159K–$231K, in line with the $177K market median.

See the full Semiconductor salary breakdown →
Apply →

Other roles at Google

  • Customer Engineer, Data/Analytics, Google Public SectorReston, VA, USA
  • Product Manager, Gemini API Models, DeepMindMountain View, CA, USA
  • Senior UX Design Manager, Search Ads UINew York, NY, USA
  • Director, Digital Demand, Scale Programs, Social, Customer AdvocacySingapore
  • Engineering Manager, PlumberNew York, NY, USA
  • Staff Software Engineer, Infrastructure, Google CloudHyderabad, Telangana, India
  • Senior Software Engineer, Infrastructure, Persistent DiskSunnyvale, CA, USA
  • Software Engineering Manager II, Google Distributed Cloud HostedSunnyvale, CA, USA
  • Senior Staff Software Engineer, Infrastructure, Google CloudSunnyvale, CA, USA
  • Software Engineer, Generative AI, MapsMountain View, CA, USA

More Semiconductor roles

  • Senior ASIC Timing Engineer, DFTNVIDIA · US, CA, Santa Clara
  • Senior Physical Design Layout EngineerNVIDIA · Israel, Yokneam
  • Senior Physical Design EngineerNVIDIA · Israel, Yokneam
  • Senior Post Silicon Validation Engineer - LPUNVIDIA · US, CA, Santa Clara
  • Physical Design EngineerNVIDIA · Israel, Yokneam
  • GPU Core Pipeline IP Verification EngineerNVIDIA · India, Bengaluru
  • ASIC Design EngineerNVIDIA · India, Bengaluru
  • Senior Power Integrity Engineer - LPU PackagingNVIDIA · Taiwan, Hsinchu
  • ASIC Verification EngineerCisco · Cairo Al Qahirah, Egypt
  • Serdes System Design Engineer/ArchitectBroadcom · USA-TX-Austin - River Place B7