Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
As a member of the inter-chip interconnect team, you will play an important role in designing ASIC/SoC hardware for AI and networking accelerators that drive the computational workloads behind Google's most important products. Our hardware accelerators power nearly every product Google offers. Our primary focus is AI acceleration.
You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will have the opportunity to solve challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.