Technical Lead, Digital Design Subsystems

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 10 years of experience working on multiple SoCs with silicon success.
• 3 years of experience in RTL coding using Verilog or Systemverilog language.
• Experience in design and multi power domains with clocking.

Preferred qualifications:

• Experience in high performance design, multi power domains with complex clocking.
• Proficient with Verilog or System Verilog language.
  
• Proficient with ASIC design methodologies for front quality checks including Lint, CDC/RDC, synthesis, DFT ATPG/Memory BIST, UPF and low power optimization/estimation.
• Proficient with chip design flow and good understanding of cross domain involving Design Verification (DV)/Design for Testability (DFT)/physical design/software.
• Proven record of multiple SoCs with silicon success.
• Participate in Static Timing Analysis (STA) closure, DV test-plan and coverage analysis of the sub-system and chip level verification.