As a Design-for-Test (DFT) Engineer, you will define, implement, and deploy design-for-test methodologies, including Scan, Memory Built-In Self-Test (MBIST), Joint Test Action Group (JTAG), and iJTAG, for digital or mixed-signal chips or Intellectual Properties (IPs). You will define DFT architecture and create DFT flows for test chips and next-generation System on Chips (SoCs) in partnership with the Design and Physical Design teams. You will also verify test logic, generate test patterns, and debug test coverage issues.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.Based on 282 disclosed Semiconductor salaries on RoleSuite, the role pays a median of $177K/year, with most offers between $142K and $206K (10th–90th percentile: $129K–$238K).
Google ranks among the higher-paying employers for this role, at a $200K median across 52 disclosed postings.
This posting lists $116K–$166K, below the $177K market median.
See the full Semiconductor salary breakdown →