Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will develop and deploy productization solutions while partnering with cross-functional teams to enable manufacturing at fabrication plants and assembly and test sites. You will help integrate System on a chip (SoC) technologies into devices and facilitate Automated Test Equipment (ATE)/System Level Testing (SLT) manufacturing testing of SoC to validate performance and screen out failing devices. You will work with cross-functional teams to ensure optimal test coverage and cost efficiencies in production to ensure quality SoCs. You will work with multiple groups to develop digital and mixed signal tests, automation methodologies, develop/support internal tools for data analysis, yield analysis, silicon debug, reliability qualification, manufacturing ramp and customer returns. You will also be a partner on releasing production test solutions into mass production.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Semiconductor Processing, or a related field, or equivalent practical experience.
- 4 years of experience in VLSI technologies, product and test engineering, and semiconductor processing.
- Experience in Integrated Circuit (IC) qualification, data review, production release, system level testing, test time reduction and yield improvement.
- Experience with Yield and Fail Pareto Analysis using JMP, Exensio, Datapower or O+.
Preferred qualifications:
- 8 years of experience in VLSI technologies, Product and Test Engineering, Semiconductor processing.
- Experience in Test and Design for test (DFT) techniques, and with structural tests such as Scan/ATPG, JTAG, Memory BIST and sensors such as PVT/temperature/current/droop sensors, etc.
- Experience with test chip design, development and testing methodologies.
- Experience with advanced packaging such as 2.5d, 3d, InFo.
- Familiar with Automatic Test Equipment (ATE) test platforms such as Advantest 93K , Teradyne UltraFlex SOC test system.
- Knowledge of reliability stress, device qualification and associated processes.