Senior DFT Design/Micro architect Engineer, Google Cloud

Google · Bengaluru, Karnataka, India

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves.

Your team designs and builds the hardware, software and networking technologies that power all of Google's services.

As a Design for Testing (DFT) micro architect/design Engineer, you define, design, analyze the DFT implementation and flow, that supports the systems that are the heart of the world's largest and most powerful computing infrastructure. The team develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Minimum qualifications:

Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
8 years of experience in the implementation and validation of DFT technologies.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).
Experience in fault modeling.
Experience in SoC cycles, silicon bringup, and silicon debug activities.

Hardware pay context

Based on 2,170 disclosed Hardware salaries on RoleSuite, the role pays a median of $135K/year, with most offers between $109K and $172K (10th–90th percentile: $91K–$208K).

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Senior DFT Design/Micro architect Engineer, Google Cloud

Minimum qualifications:

Preferred qualifications:

Hardware pay context

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