In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of the TPU team that builds Machine Learning Accelerator ASICs for Google and positively impact Google’s products and billions of Google users across the globe.
In this role you will be working on ASIC development, validation, software, tools, and methodologies and have the ability to push the boundaries of chip-development and hardware/software (HW/SW) integration and validation.
Support cross-functional work streams focused on end-to-end HW/SW integration and validation to demonstrate HW, SW, and system functionality and performance. Help the chip team accomplish key silicon development criteria, meet chip and system schedules and achieve readiness for production in various silicon and system validation environments.
You may write firmware, RTL, scripts, or test content to integrate and demonstrate subsystem and system functionality. You will validate this functionality on simulation, emulation, or post-silicon environments.
Based on 7,725 disclosed Software salaries on RoleSuite, the role pays a median of $158K/year, with most offers between $123K and $199K (10th–90th percentile: $101K–$236K).
This posting lists $116K–$166K, below the $158K market median.
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