Senior SoC Hardware Quality and Reliability Engineer

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, related fields, or equivalent practical experience.
• 8 years of experience in hardware engineering, with a focus on authoring technical specifications, reviewing electrical layouts, and driving verification of semiconductor tests or validation platforms.
• Experience driving deliverables and managing quality standards with external layout vendors, board design houses, or hardware component suppliers across multiple global geographies.
• Experience working within specialized semiconductor reliability or test laboratories including configuring component Burn-In ovens, high-power stress load boards, ESD simulators, and Latch-Up test setups.
• Experience managing engineering hardware delivery schedules, tracking cross-functional milestones, and meeting New Product Introduction (NPI) timelines.

Preferred qualifications:

• Master's degree in Electrical Engineering, Materials Science, or related fields.
• Experience managing the design execution cycle of complex multi-layer test vehicles through third-party design houses or layout vendors from concept sign-off to laboratory delivery.
• Experience defining and verifying electrical correlation baselines between environmental stress setups and High-Volume Manufacturing (HVM) ATE environments.
• Deep familiarity with JEDEC silicon qualification hardware standards and how they dictate physical board testing constraints.
• Strong background analyzing the quality of stress factors, including power distribution networks (PDN), signal integrity degradation across extended thermal loops, and transient load behavior during reliability cycles.