Senior RTL Design Engineer, Google cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will join a team developing Application-Specific Integrated Circuits (ASICs) to accelerate Machine Learning (ML) computation in data centers. You will collaborate with Architecture, Verification, Power and Performance, and Physical Design teams to specify and deliver quality designs for next-generation accelerators. You will solve technical problems through micro-architecture innovation and evaluate design trade-offs between performance and power.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in Application-Specific Integrated Circuit/System on a chip (ASIC/SoC) development with Verilog/SystemVerilog.
• Experience in micro-architecture and design of IPs and Subsystems.
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• Experience with scripting languages (e.g., Python or Perl).
• Experience in SoC designs and integration flows.
• Knowledge of high performance and low power design techniques.
• Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.