SemiJobs
RoleSuite
CompaniesRemoteAboutMethodologyContactPrivacy
Updated 2026-06-30 17:00 UTC·© 2025–2026 RoleSuite
← Back to listings

Design Verification Engineer III, Multimedia, Silicon

Google · Bengaluru, Karnataka, India

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Multimedia Hardware team designs and validates high-performance subsystems that power Google's consumer devices and infrastructure. We focus on the video, image, and display processing technologies, including Image Signal Processors (ISP), Display Processing Units (DPU), and hardware CODECs (encoder/decoder). Our mission is to deliver industry-leading multimedia experiences with optimal power, performance, and area.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
  • 4 years of experience verifying digital logic at RTL using SystemVerilog for ASICs.
  • Experience coding in SystemVerilog and using standard verification methodologies (i.e., UVM).
  • Experience verifying digital IP or subsystems.

Preferred qualifications:

  • Master's or PhD degree in Electrical Engineering or Computer Science.
  • Experience verifying multimedia or image processing hardware components, specifically Image Signal Processors (ISPs), Display Processing Units (DPUs), display interfaces, or Video CODECs.
  • Experience with high-speed bus protocols (e.g., AXI, AHB) and memory subsystems.
  • Experience with formal verification (SystemVerilog Assertions (SVA)) or emulation platforms (e.g., Palladium, ZeBu).
  • Excellent scripting skills (Python, Perl, or Shell) for automation of verification flows.
  • Excellent problem-solving, communication, and collaboration skills.

Semiconductor pay context

Based on 275 disclosed Semiconductor salaries on RoleSuite, the role pays a median of $180K/year, with most offers between $147K and $206K (10th–90th percentile: $132K–$238K).

Google ranks among the higher-paying employers for this role, at a $200K median across 54 disclosed postings.

See the full Semiconductor salary breakdown →
Apply →

Other roles at Google

  • Customer Engineer, Platform, DACH, FSI, Google CloudMunich, Germany
  • Lead Group Product Manager, Marketing Technology PlatformMountain View, CA, USA
  • Software Engineering Manager, Android Automotive AI/MLKraków, Poland
  • Digital Marketing Strategist, gTech Ads (English, Korean)Seoul, South Korea
  • Product Manager II, AI Crisis ResilienceTel Aviv, Israel
  • Federal Go-To-Market Lead, AI Infrastructure, Google Public SectorReston, VA, USA
  • Practice Customer Engineer III, Cloud AI, Google CloudSingapore
  • Strategic Partner Development Principal Lead, Android Platform Partnerships (Mandarin, English)Taipei, Taiwan
  • Regional Product Lead, PSA AppsSingapore
  • Senior Developer Relations Engineer, AI InfrastructureSunnyvale, CA, USA

More Semiconductor roles

  • 2026 Graduate Silicon EngineerGraphcore · Bristol, UK
  • Early Career PMU Digital Design EngineerApple · Swindon
  • Substation Physical Designer (Inventor)Jobgether · Canada
  • Physical Design CAD EngineerNVIDIA · Israel, Yokneam
  • Senior Mixed Signal Design Verification EngineerNVIDIA · Taiwan, Hsinchu
  • FPGA Design Technical Leader- Ethernet,PCIe, System Verilog, Xilinx- 12+ YearsCisco · Bangalore, India
  • Silicon Packaging Design EngineerIntel · Malaysia, Penang
  • Staff Engineer, ASIC Development Engineering (IO, Layout)Sandisk · Bengaluru, KA, India
  • Staff Engineer, ASIC Development Engineering Sandisk · Bengaluru, KA, India
  • Principal Engineer, ASIC Development Engineering (ASIC SoC Validation with protocol experience in DDR, PCIe) with 8 to 12 yearsSandisk · Bengaluru, KA, India