Principal ASIC Design Verification Engineer

Jobgether · US

This position is listed on behalf of a partner company, which manages all applications and next steps. Our partner is seeking a Principal ASIC Design Verification Engineer based in the United States.

This is a senior technical leadership role focused on verifying the functionality, performance, and robustness of cutting-edge custom silicon designed for advanced space systems.
You will play a key role in defining verification strategy and building scalable methodologies for first-generation ASIC development.
The role is highly hands-on, requiring deep engagement in SystemVerilog/UVM environments and complex SoC-level verification.
You will collaborate closely with architecture, RTL design, DFT, firmware, and silicon validation teams to ensure full-chip correctness.
This position offers the opportunity to influence verification best practices and shape the future of high-reliability space-grade silicon.
You will also contribute to silicon bring-up and post-silicon validation in a fast-paced, mission-driven engineering environment.
The work is high-impact, involving large-scale systems built for demanding performance and extreme operating conditions.

Accountabilities:

  • Develop and execute comprehensive verification strategies across block, subsystem, and full-chip levels, ensuring functional correctness and design robustness.
  • Build and maintain advanced SystemVerilog/UVM testbenches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Define and implement constrained-random and directed test plans to validate corner cases, stress scenarios, and system-level functionality.
  • Write and integrate SystemVerilog Assertions (SVA) and apply formal verification techniques where appropriate.
  • Run large-scale simulation regressions, triage failures, and perform root-cause analysis in collaboration with RTL designers.
  • Manage functional, code, and assertion coverage closure to ensure readiness for tape-out sign-off.
  • Oversee regression infrastructure, CI pipelines, and simulation environments to enable high-throughput verification and fast debug cycles.
  • Participate in architecture reviews and influence design-for-verification (DFV) methodologies and improvements.
  • Collaborate cross-functionally with RTL, DFT, firmware, physical design, and validation teams to ensure end-to-end system verification.
  • Support silicon bring-up and post-silicon debug using test reuse, diagnostics, and failure analysis.
  • Contribute to hiring processes and help evaluate ASIC engineering talent.
  • Drive continuous improvement of verification methodologies and support external IP integration when required.
  • Take ownership of large and complex verification efforts across subsystems and full-chip architectures.

    • Requirements:

    • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
    • 10+ years of experience in ASIC/SoC design verification.
    • Strong expertise in SystemVerilog, UVM, RTL design principles, and digital hardware verification flows.
    • Experience with industry-standard simulators (VCS, Xcelium, Questa) and debugging tools (Verdi, SimVision).
    • Proficiency in scripting languages such as Python, Perl, or TCL for automation and infrastructure development.
    • Deep understanding of constrained-random verification, functional coverage, and SystemVerilog Assertions.
    • Experience with regression management, CI/CD systems, version control (Git), and gate-level simulation.
    • Ability to develop reference models and support complex verification environments.
    • Familiarity with embedded systems, including C/C++ firmware or bare-metal development.
    • Knowledge of standard interfaces such as AXI, AHB, and APB.
    • Exposure to post-silicon validation planning and execution is highly valued.
    • Strong collaboration and communication skills, with experience working across multi-disciplinary engineering teams.
    • Bonus: experience with low-power verification, analog behavioral modeling, physical design flows, or space/telecom/RF systems.

      • Benefits:

      • Competitive base salary ranging from $190,000 – $285,000 USD, plus equity participation.
      • Comprehensive health coverage including medical, dental, and vision insurance.
      • Paid time off, holidays, and flexible parental leave policies.
      • Life insurance and additional employee protection programs.
      • Equity opportunities in a high-growth, venture-backed deep-tech environment.
      • Exposure to cutting-edge space hardware programs and first-of-a-kind silicon development.
      • Collaborative, high-performance engineering culture with significant technical ownership.
      • Opportunity to work on mission-critical systems shaping next-generation space infrastructure.

Semiconductor pay context

Based on 264 disclosed Semiconductor salaries on RoleSuite, the role pays a median of $179K/year, with most offers between $144K and $206K (10th–90th percentile: $132K–$238K).

This posting lists $190K–$285K, above the $179K market median.

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