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Semiconductor · sourced direct from Google

Semiconductor at Google.

Google currently has 48 open semiconductor roles, concentrated in Sunnyvale, Bengaluru and New Taipei (38 remote, 8 hybrid), spanning entry through senior levels. Apply at the source — RoleSuite links straight to Google's official careers page, no intermediary.

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48 roles

TPU RTL Design Engineer, Networking, Inter-Chip InterconnectsSunnyvale, CA, USA CPU Performance Architect, SiliconNew Taipei, Banqiao District, New Taipei City, Taiwan Design Verification Engineer, TPU, Silicon, Google CloudBengaluru, Karnataka, India Design Verification EngineerMountain View, CA, USA ASIC Formal Verification Engineer, Google CloudSunnyvale, CA, USA Senior CPU Design Verification Engineer, EmulationAustin, TX, USA Silicon Validation and Debug EngineerTel Aviv, Israel Senior Silicon Engineer- P and D- (gCPU), Design Verification (multiple openings)Austin, TX, USA Silicon Design Verification Engineer, Google CloudBengaluru, Karnataka, India Hardware Emulation Engineer, Google CloudSunnyvale, CA, USA Junior Silicon DFT Engineer, Google CloudTel Aviv, Israel DFT Engineer III, Cloud SiliconBengaluru, Karnataka, India Design Verification Engineer, Multimedia, SiliconNew Taipei, Banqiao District, New Taipei City, Taiwan ASIC Digital Design Engineer II, Silicon EngineeringBengaluru, Karnataka, India ASIC Design Verification Engineer, ComputeSunnyvale, CA, USA Senior TPU RTL Design Engineer, Networking, Inter-Chip InterconnectsSunnyvale, CA, USA CPU Design Verification EngineerNew Taipei, Banqiao District, New Taipei City, Taiwan RTL Design Engineer, Machine Learning AcceleratorsSunnyvale, CA, USA Senior Silicon Validation Engineer, Volume Production and YieldNew Taipei, Banqiao District, New Taipei City, Taiwan SoC DFT Engineer, Google CloudSunnyvale, CA, USA IP DFT EngineerSunnyvale, CA, USA ASIC Physical Design Tools, Flows, Methodologies ManagerSunnyvale, CA, USA Physical Design EngineerSunnyvale, CA, USA Senior SOC DFT Engineer, Google CloudTel Aviv, Israel Tensor SOC Performance Design Verification EngineerBengaluru, Karnataka, India ASIC Design Verification Technical Lead, TPUSunnyvale, CA, USA RTL Design Engineer, TPU Integration and AutomationSunnyvale, CA, USA ASIC Formal Verification Engineer, TPU ComputeSunnyvale, CA, USA Senior ASIC Design Engineer, Google CloudSunnyvale, CA, USA Staff Silicon Physical Design Engineer, Quantum AIMountain View, CA, USA Silicon Validation and Automation EngineerTel Aviv, Israel Silicon Physical Design CAD EngineerNew Taipei, Banqiao District, New Taipei City, Taiwan ASIC RTL Design Engineer III, SiliconBengaluru, Karnataka, India TPU RTL Design Engineer, CloudSunnyvale, CA, USA ASIC Design Verification Engineer, Google CloudSunnyvale, CA, USA RTL Design Engineer, TPU ComputeSunnyvale, CA, USA ASIC Design Verification Engineer, TPU ComputeSunnyvale, CA, USA ASIC Design Verification Engineer, TPU CloudSunnyvale, CA, USA Lead CPU Design Verification Engineer, SiliconPortland, OR, USA Silicon Physical Design Engineer, Google CloudBengaluru, Karnataka, India CPU Logic Design Engineer, Google CloudTel Aviv, Israel Physical Design Technical Lead, ASIC, TPUSunnyvale, CA, USA TPU RTL Design EngineerSunnyvale, CA, USA Silicon Design Verification EngineerBengaluru, Karnataka, India Senior CPU Performance ArchitectMountain View, CA, USA Platform and Chassis ASIC Architect, SiliconBengaluru, Karnataka, India Analog Design Engineer, Google CloudSunnyvale, CA, USA Technical Lead Manager, Machine Learning, Memory Subsystem DesignSunnyvale, CA, USA

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